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| 1 ? fn8204.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. preliminary x9470 rf power amplifier (pa) bias controller features ? programmable bias cont roller ic for class a and ab ldmos power amplifiers ? adaptive system on chip solution ? bias current calibration to better than 4% using reference trim dcp ? automatic bias point tracking and calibration ? i dq sensing and tracking ?programmable instrume ntation amplifier to scale wide range of i dq ?programmable gate bias driver ?all programmable settings are nonvolatile ?all settings recalled at power-up. ? 28v maximum v dd ? 2 wire interface for programming bias setting and optimizing i dq set point ? bias level comparator ? shutdown control pin for pa signal ? slave address to allo w for multiple devices ? 24-pin tssop package ? applications: cellular base stations (gsm, umts, cdma, edge), td d applications, point- to-multipoint, and other rf power transmission systems description the intersil x9470 rf pa bias controller contains all of the necessary analog components to sense the pa drain current through an external sense resistor and automatically control the gate bias voltage of an ldmos pa. the external sense resistor voltage is am- plified by an instrumentation amplifier and the output of the amplifier along with an external reference voltage is fed to the inputs of a comparator. the comparator out- put indicates which direction the ldmos gate bias volt- age will move in the next calibration cycle. system calibration is accomplished by enabling the x9470 and providing a clock to the scl pin. the ldmos drain cur- rent can be maintained constant over temperature and aging changes by periodic calibration. the vout pin can be used to monitor the average power by tracking the drain current. up to eight x9470 or additional inter- sil digital potentiometers can be controlled via a two- wire serial bus. typical application a0 a2 vcc vss v+ agnd comparator choke rf pa in r sense v dd v ref v sense+ v bias inc/dec instrumentation amplifier ? v cs v out v sense? r ref rw ref rl ref shdn + ? eeprom scl sda a1 vbias control vref control i2c interface control & status registers rf out rh ref r bias vp rh bias rl bias rw bias filter v bias (unbuffered) rf impedance matching c bulk class a example data sheet march 8, 2005
2 fn8204.0 march 8, 2005 pin configuration ordering information pin descriptions part number temperature range package X9470V24I -40c to 85c 24-lead tssop tssop pin symbol brief description 1v sense+ positive sense voltage input terminal 2rh ref upper terminal of potentiometer, called the r ref potentiometer. the voltage appl ied to this pin will determine the upper voltage limit of the adjustment fo r the up/down threshold of the comparator. 3rl ref lower terminal of potentiometer, called the r ref potentiometer. the voltage appl ied to this pin will determine the lower voltage limit of the adjustment for the up/down th reshold of the comparator. 4rw ref wiper terminal of potentiometer, called the r ref potentiometer. the voltage on this pin will be the threshold for the up/down comparator. also referred to as the v ref of the comparator. 5agnd analog ground to allow single point grounding external to the package to minimize digital noise. 6 vss system (digital) ground reference 7cs chip select. this input enables bias calibration adjustments to the r bias potentiometer. cmos input with in- ternal pull-down. 8scl dual function. function 1: the increment control input. increments or decrements the rbias potentiometer. function 2: serial data clock input. requires external pull-up. 9sda serial data input. bi-directional 2-wire interface. requires external pull-up. 10 rh bias upper terminal of potentiometer, called the r bias potentiometer. the voltage applie d to this pin will determine the upper limit of the bias voltage to the pa (or v bias pin). 11 rw bias wiper terminal of potentiometer, called the r bias potentiometer. this voltage is the equivalent to the unbuf- fered voltage that will appear at the v bias pin. 12 rl bias lower terminal of potentiometer, called the r bias potentiometer. the voltage applie d to this pin will determine the lower limit of the bias voltage to the pa (or v bias pin). 13 a0 external address pin which allows for a hardw are slave address selection of this device. this pin has an internal pull-down. 14 a1 external address pin which allows for a hardw are slave address selection of this device. this pin has an internal pull-down. 15 a2 external address pin which allows for a hardw are slave address selection of this device. this pin has an internal pull-down. 16 vss system (digital) ground reference 17 v bias this is the bias output voltage pin and is used to drive the filter network to the pa gate. 18 v cc system (digital) supply voltage 19 v cc system (digital) supply voltage 20 v + positive voltage supply for the instrum entation amplifier and other analog circuits. 21 v out instrumentation amplifier output that is 20x or 50x the voltage across the rsense pins. 22 inc/dec status output that indicates the st ate of the comparator. when this pin is high, the rbias potentiometer will increment; when the pin is low, the rbias potentiometer will decrement. this pin is open drain and requires external resistor pull-up. 23 shdn shutdown the output op amp. when shdn is active (high), the v bias pin is pulled low. 24 v sense- negative sense voltage input terminal v out rw ref v+ tssop 1 2 3 4 5 6 7 14 20 19 18 17 16 15 x9470 v sense+ v sense- rh ref rl ref vss agnd shdn inc/dec v cc a2 rh bias v cc sda scl v bias vss cs 8 9 10 13 rl bias rw bias 11 12 a0 a1 24 23 22 21 x9470 3 fn8204.0 march 8, 2005 absolute maximum ratings* voltage on v+ (referenced to agnd) ...................... 7v voltage on vcc (reference to vss) .......... .............. 7v voltage on all rh, rw, rl pins (reference to ag nd): ........................................... 7v voltage on vsense+ or vsense- (reference to agrnd).......................... 30v voltage on sda, cs, scl, shdn (reference to agnd) .......... ..... -0.3v to (vcc + 0.3v) current into output pin: .......................................... 5ma continuous power dissipation: ....................... 500mw operating temperature range:.............. -40 c to +85 c junction temperature: ..........................................150 c storage temperature ........................ -65 c to +150 c lead temperature (soldering, 10 seconds): ..... 300 c *comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specifi- cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics instrumentation amplifier recommended operating conditions: (vcc, v+ = 4.75 to 5.25v; vsense+, vsense- = 26v; t a = -40c to +85c, unless otherwise noted.) symbol parameter limits test conditions/notes min. typ. max. units v in (10) common mode input voltage on v sense+ and v sense- pins 20 28 v gain 1 gain from v sense to v out (2) 20 v/v measured with status register bit sr0 = 0 gain 2 gain from v sense to v out (2) 50 v/v measured with status register bit sr0 = 1 v range1 differential voltage sense range between v sense+ and v sense- for gain 1 60 90 mv gain = 20 v range2 differential voltage sense range between v sense+ and v sense- for gain 2 40 60 mv gain = 50 v os input offset voltage 0.5 mv v sense = 40mv to 90mv t a = 25c av1 gain 1 error gain = 20 (4) 1.5 % v sense = 60mv to 90mv t a = 25 to 85c, gain = 20 av2 gain 2 error gain = 50 (4) 1.5 % v sense = 40mv to 60mv t a = 25 to 85c, gain = 50 avt1 total error, gain 1 gain = 20 (5) -6 1.5 6 % v sense = 60mv to 90mv t a = 85c, gain = 20 10 % v sense = 60mv to 90mv t a = 25 to 85c, gain = 20 avt2 total error, gain 2 gain = 50 (5) -6 1.5 6 % v sense = 40mv to 60mv t a = 85c, gain = 50 10 % v sense = 40mv to 60mv t a = 25 to 85c, gain = 50 at long term drift 2 % avt1 or avt2 sr (10) slew rate of instrumentation amp 0.2 v/s ? v sense = 20mv step, cout = 10pf measured at v out (1,3) x9470 4 fn8204.0 march 8, 2005 comparator recommended operating conditions: (vcc, v+ = 4.75 to 5.25v; vsense+, vsense- = 26v; t a = -40c to +85c, unless otherwise noted.) t settle (10) setting time of instrumentation amp 5.0 s ? v sense = 20mv step, cout = 10pf, settling to 1% of final value measured at v out (1,3) cmrr common mode rejection ratio 40 db for both gain 1 and gain 2 psrr power supply rejection ratio 55 db for both gain 1 and gain 2 v out range v out voltage swing 0.3 1.8 v gain = 20 0.3 3.0 v gain = 50 v out noise (10) v out voltage noise, rms 3 mv gain = 20 i vsense (10) v sense+ , v sense- input bias current 250 a t a = 25c c vsense (10) v sense+ , v sense- input capacitance 10 pf each input symbol parameter limits test conditions/notes min. typ. max. units vol output voltage low on the inc/dec pin 0.4 v iol = 1ma io (10) output sink current 3 ma inc/dec pin, open drain vos (10) input hysteresis 20 mv vcc = 5 v tpd (10) response time for propagation delay 2 s inc/dec pin with 2k ? pull up electrical characteristics instrumentation amplifier (continued) recommended operating conditions: (vcc, v+ = 4.75 to 5.25v; vsense+, vsense- = 26v; t a = -40c to +85c, unless otherwise noted.) symbol parameter limits test conditions/notes min. typ. max. units vref dcp circuit block recommended operating conditions: (vcc, v+ = 4.75 to 5.25v; vsense+, vsense- = 26v; t a = -40c to +85c, unless otherwise noted.) symbol parameter limits test conditions/notes min. typ. max. units r total end to end resistance 8 10 12 k ? number taps or positions 64 v rh rh ref terminal voltage agnd v + vagnd = 0v v rl rl ref terminal voltage agnd v + vagnd = 0v v rw rw ref terminal voltage agnd v + vagnd = 0v power rating (10) 2.5 mw r total = 10k ? resolution (10) 1.6 % absolute linearity (6) -0.2 +0.2 mi (8) relative linearity (7) -0.2 +0.2 mi (8) x9470 5 fn8204.0 march 8, 2005 bias adjustment dcp circuit block recommended operating conditions: (vcc, v+ = 4.75 to 5.25v; vsense+, vsense- = 26v; t a = -40c to +85c, unless otherwise noted.) r total temperature coefficient (10) 300 ppm/c ratiometric temperature coefficient (10) -20 +20 ppm/c c in (10) potentiometer capacitances on rh ref and rl ref 10 pf symbol parameter limits test conditions/notes min. typ. max. units r total end to end resistance variation 8 10 12 k ? with 20% variation number taps or positions 256 v rh voltage at the rh bias terminal voltage agnd v + vagnd = 0v v rl voltage at the rl bias terminal voltage agnd v + vagnd = 0v v rw voltage at the rw bias terminal voltage agnd v + vagnd = 0v power rating (10) 2.5 mw r total = 10 k ? resolution (10) 0.4 % absolute linearity (6) -1.0 +1.0 mi (8) relative linearity (7) -1.0 +1.0 mi (8) r total temperature coefficient (10) 300 ppm/c ratiometric temperature coefficient (10) -50 50 ppm/c c in (10) potentiometer capacitances on rh bias and rl bias 10 pf vref dcp circuit block recommended operating conditions: (vcc, v+ = 4.75 to 5.25v; vsense+, vsense- = 26v; t a = -40c to +85c, unless otherwise noted.) symbol parameter limits test conditions/notes min. typ. max. units vbias output voltage follower recommended operating conditions: (vcc, v+ = 4.75 to 5.25v; vsense+, vsense- = 26v; t a = -40c to +85c, unless otherwise noted.) symbol parameter limits test conditions/notes min. typ. max. units v os input offset voltage 10 mv v osdrift (10) offset voltage temperature coefficient 10 v/c t a = -40 to +85c sr output slew rate on v bias 0.5 v/ sr l = 10k ? , 1nf, ? v bias = 20mv v bias voltage output swing 1.5 v cc - 0.5 v i out = 10ma t s (10) settling time 2 s final value 1%, r l = 10k ? , 1nf, ? v bias = 20mv t shdn time for shdn pin (delay) valid 0.1 1.0 s psrr power supply rejection ratio 45 55 d b vcc supply v cc = 4.75 to 5.25v x9470 6 fn8204.0 march 8, 2005 d.c. operating characteristics recommended operating conditions: (vcc, v+ = 4.75 to 5.25v; vsense+, vsense- = 26v; t a = -40c to +85c, unless otherwise noted.) notes: (1) v out is a high impedance output intended for light loads only. (2) gain at v out is set to 20 by default. (3) value given is for v out . the v bias output will depend on the v bias potentiometer which is initially loaded with a zero value, then fol- lowed by the loading of the final value from e 2 memory. (4) gain error excludes the contribution of the input offset voltage error. (5) total error includes the contributions of gain error and input offset voltage error. (6) absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (v w(n) (actual) - v w(n) (expected)) (7) relative linearity is a measure of the error in step size between taps = v w(n+1) - [v w(n) + ml] (8) 1 ml = minimum increment = r tot /63 or r tot /255. (9) typical values are for t a = 25c and nominal supply voltage, vcc = 5v. (10) this parameter is not 100% tested. input voltage range 1.5 v cc - 0.5 v c l (10) load capacitance 1 nf c in (10) capacitances on shutdown pin 10 pf r out (10) output impedance 3 ? at 5mhz, 1nf load symbol parameter limits units test conditions min. typ. max. i cc1 (9) v+ active current 1 3 ma cs = v cc - 0.3v, and scl @ max. t cyc, sda = v cc - 0.3v, shdn inactive i cc2 (9)(10) v cc active current 5 25 ma i sb (9) standby supply current (v cc , v+) 1.5 ma cs = v il , and scl inactive (no clock) , sda = v il , shdn active i li cs, sda, scl, shdn rh, rl, rw, inc/dec vout, input leakage -10 10 a v in = vss to v cc v ih (10) cs, sda, scl, shdn, a0, a1, a2 high voltage v cc x 0.7 v cc + 0.5 v v il (10) cs, sda, scl, shdn, a0, a1, a2 low voltage -0.5 v cc x 0.3 v c in (10) cs, sda, scl, shdn, a0, a1, a2 capacitance 10 pf v cc = 5v, v in = vss, t a = 25c, f = 1mhz vbias output voltage follower recommended operating conditions: (vcc, v+ = 4.75 to 5.25v; vsense+, vsense- = 26v; t a = -40c to +85c, unless otherwise noted.) symbol parameter limits test conditions/notes min. typ. max. units x9470 7 fn8204.0 march 8, 2005 bias adjustment circuit block a.c. operating characteristics recommended operating conditions: (vcc, v+ = 4.75 to 5.25v; vsense+, vsense- = 26v; t a = -40c to +85c, unless otherwise noted.) a.c. timing note: (11) mi in the a.c. timing diagram refers to the minimum incremental change in the v bias output due to a change in the wiper position. symbol parameter limits units min. typ. (9) max. t cl cs to scl setup 100 ns t ld vsense change to inc/dec change 5 s t ll scl low period 1.5 s t lh scl high period 1.5 s t lc (10) scl inactive to cs inactive 100 ns t iw (10)(11) scl to v bias change 3 s t cyc scl cycle time 3 s t r , t f (10) scl input rise and fall time 500 ns cs scl inc/dec v bias t ci t il t ih t cyc t id t iw t ic t f t r 10% 90% 90% (vsense+ ? vsense-) x9470 8 fn8204.0 march 8, 2005 ac specifications note: (12) cb = total capacitance of one bus line in pf. timing diagrams bus timing write cycle timing symbol parameter min. max. unit f scl scl clock frequency 0 400 khz t in (10) pulse width suppression time at inputs 50 ns t aa (10) scl low to sda data out valid 0.1 0.9 s t buf (10) time the bus must be free before a new transmission can start 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 200 ns t hd:dat data in hold time 200 ns t su:sto stop condition setup time 0.6 s t dh (10) data output hold time 50 ns t r (10) sda and scl rise time 20 +.1cb (12) 300 ns t f (10) sda and scl fall time 20 +.1cb (12) 300 ns cb (10) capacitive load for each bus line 400 pf t su:sto t dh t high t su:st t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r scl sda t wc 8th bit of last byte ack stop condition start condition x9470 9 fn8204.0 march 8, 2005 power-up timing note: delays are measured from the time v cc is stable until the specified operation can be initiated. these parameters are not 100% tested. proper recall of stored wiper setting requires a v cc power-up ramp that is monotonic and with noi se or glitches < 100mv. it is important to correctly sequence voltages in an ldmos amplifier circuit. for the x9470 typical application, the v cc , then v+ pins should be powered before the v dd of the ldmos to prevent ldmos dama ge. under no circumstances should the v dd be applied to the ldmos device before v cc and v+ are applied to the x9470. dcp default power-up tap positions (shipped from factory) nonvolatile write cycle timing note: t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile wr ite by the user, unless a cknowledge polling is used. symbol paramete rmin.max.unit t r v cc (10) v cc power-up rate 0.2 50 v/ms vref dcp 0 bias adjust dcp 0 symbol parameter min. typ. (1) max. unit t wc (10) write cycle time 5 10 ms x9470 10 fn8204.0 march 8, 2005 detailed pin descriptions supply pins digital supplies vcc, vss the positive power supply and ground for the dcp digital control sections. vss is normally tied to digital ground. the x9470 is provided with separate digital and analog power supply pins to better isolate digital noise from the analog section. analog supplies v+, agnd the positive analog supply and ground for the instru- mentation amplifier (ia). the analog supply ground is kept separate to allow an external single point connec- tion. v+ can be a separate supply voltage from vcc, or vcc can be filtered before connection to v+. bias adjustment circuit block pins rh bias , rl bias , and rw bias for vbias adjust- ments. these pins are the connections to a intersil digitally controlled potentiome ter (xdcp?) or r bias potenti- ometer. rh bias is connected to the most positive ref- erence, and the rl bias is connected to the least positive reference voltage. the potentiometer has a resolution of 256-taps and typical r total of 10k ? . so for example, to provide 4mv resolution, the voltage dif- ference applied to the rh bias and rl bias pins must be 1.024v. the rw bias value can be stored in non- volatile memory and recalled upon power-up. serial clock (scl). this is a dual function input pin. the state of the cs pin determines the functionality. function 1: scl is a negative edge-triggered control pin of the r bias potentiometer. toggling scl will either increment or decrement the wiper in the direction indicated by the logic level on the inc/dec pin. cs must be high for this function. function 2: scl is the serial bus clock for serial bus interface. cs must be low for this function. chip select (cs). calibration enable. the cs input is the enable bias adjustments. when the cs is high (enabled) and a scl pulse is present, the wiper position on the r bias potentiometer will automatically update with either an increment or dec- rement of one tap position according to inc/dec sig- nal from the comparator. when cs is low (disabled), the wiper counter of the xdcp will hold the last wiper position until cs is enabled again and the wipe r position is updated. inc/dec monitor pin the up or down monitor pin (inc/dec ) indicates the state of the comparator. this signal indicates that the instrumentation amplifier output voltage is higher or lower than the voltag e level set by the rw ref pin. the output is used to indicate the direction that the gate bias voltage needs to move to reach the target bias voltage. sense and scale block pins v sense+ and v sense- these are the input pins to the ia circuit. these pins are used to determine the change in voltage across the the external drain sense resistor of an rf power amplifier. rh ref , rl ref , and rw ref . pa bias set point. the pa bias reference voltage is controlled by a 64- tap (10k ? typical r total ) potentiometer, called the r ref potentiometer. the voltages applied to rh ref and rl ref will determine the range of adjustment of the reference voltage level (vref) for the compara- tor. the resolution of the comparator reference is the difference of the voltages applied to rh ref and rl ref divided by 63. the position of the wiper (rw ref ) is controlled via serial bus. the rw ref value can be stored in non-volatile memory and recalled upon power-up. rw ref is also an input signal used as a scaling volt- age (vref) to set the appropriate i dq of an rf power amplifier. v ref can be derived from an external volt- age divider or from a baseband processor or similar microcontroller. v ref can be set permanently or changed dynamically using the potentiometer for vari- ous pa operating points. v out this pin is the output of the ia, which reflects a 20x or 50x gain of the input signal (voltage across the vsense pins). it can be used to indicate the magnitude of the drain current envelope when rf is present. x9470 11 fn8204.0 march 8, 2005 output block pins v bias the v bias is the gate bias voltage output. it is buffered with a unity gain amplifier and is capable of driving 1nf (typical) capacitive loads. this pin is intended to be connected through an rf fil- ter to the gate of an ldmos power transistor. the voltage of v bias is determined by the xdcp?s value of the r bias resistor. other pins shdn shdn is an input pin that is used to shutdown the v bias output voltage followe r. when the shdn pin is high, the v bias pin is pulled to vss. when the device is shutdown, the current r bias wiper position will be maintained in the wiper counter register. when shut- down is disabled, the wiper returns to the same wiper position before shutdown was invoked. note that when the device is taken out of shutdown mode (shdn goes from high to low), t he cs input must be cycled once to enable calibration. sda serial bus data input/output. bi-directional. external pullup is required. a0, a1, a2 serial bus slave address pi ns. these pins are used to defined a hardware slave ad dress. this will allow up to 8 of the x9470?s to be shared on one two-wire bus. these are useful if several x9470?s are used to control the bias voltages of several ldmos power transis- tors in a single applicati on. default hardware slave address is ?000? if left unconnected due to internal pull-down resistor. typical application the x9470 can be used along with a microprocessor and transmit control chips to control and coordinate fet biasing (see figure 1). the cs, scl, and sda sig- nals are required to contro l the x9470 bias adjustment circuit block. an internal r wref voltage is provided via a programmable voltage divider between the rh ref and rl ref pins and is used to set the voltage reference of the comparator. the shutdown (shdn) and bias volt- age indicators (inc/dec ) are additional functions that offer fet control, monitoring, and protection. typically, the closed loop set up of the x9470 allows for final calibration of a power amplifier at production test. the cs and scl pins are used to perform this calibra- tion function. once in a base station, the amplifier can then be re-calibrated any time that there is no rf signal present. the bias setting block can also be used open loop to adjust gate bias or can be shutdown using the shdn pin. the sense and sc ale block can be used for amplifier power monitori ng diagnostics as well. the range of the drain bias current operating point of the ldmos fet is set by an external reference across the reference potentiometer. the wiper of the potentiometer sets the trip point for comparison with v p , the amplified voltage across r sense , the drain resistor. the output of the comparator causes the r bias potentiometer to increment or decrement auto- matically on the next scl clock cycle. this r bias potentiometer is configured as a voltage divider with a buffered wiper output whic h drives the gate voltage of an external ldmos fet. once the optimum bias point is reached, the r bias value is latched into a wiper counter register. again, the v bias gate voltage can be updated continuously or periodically depending on the system requirements. both terminals of the r bias potentiometer are access- ible and can be driven by external reference voltages to achieve a desired i dq vs. gate voltage resolution, as well as supporting temperature compensation circuitry. in summary, the x9470 provi des full flexibility on set- ting the operating bias point and range of an external rf power amplifier for gsm, edge, umts, cdma or other similar applications. x9470 12 fn8204.0 march 8, 2005 figure 1. typical application x9470 functiona l description this section provides detail description of the following: ? sense and scale block description ? bias adjustment control block description ? output block description ? bias adjustment and storage description sense and scale block the sense and scale circuit block (figure 2) imple- ments an instrumentation amplifier whose inputs (v sense+ and v sense- ) are across an external sense resistor in the drain circuit of an rf power fet. v sense+ is connected to v dd , the drain voltage source for the rf power fet, and v sense- pin is connected to the other end the external sense resistor. an internal instrumentation amplifier (ia) will sense the ? v and amplify it by a gain factor of k 1 (see equation 1). the resulting output is compared with v ref at the comparator. v ref can be a fixed reference voltage or adjusted by using the 64-tap digital potentiometer. the output of the comparator is used to increment or dec- rement the r bias potentiometer in the bias adjust- ment circuit block. the gain factor k 1 is designed such that the sense and scale block will set the bias adjustment circuit block to operate in a given voltage range (mv) vs. drain current adjustment (ma). the output of the ia is also available at the pin vout to enable drain current monitoring. the gain at vout is fixed at a factor of k 2 , lower than k 1 so that high i dq currents will not cause satura tion of the vout signal. the equation for vout is given as: bias adjustment circuit block there are three sections of this block (figure 3): the input control, counter and decode section (1), the resistor array (2); and the non-volatile register (3). the input control section oper ates just like an up/down counter. the input of the counter is driven from the output of the comparator in the sense and scale block and is clocked by the scl signal. the output of this counter is decoded to select one of the taps of a 256- tap digital potentiometer. a0 a2 vcc vss v+ agnd comparator choke rf pa in r sense v dd v ref v sense+ v bias inc/dec instrumentation amplifier ? v cs v out v sense? r ref rw ref rl ref shdn + ? eeprom scl sda a1 vbias control vref control i2c interface control & status registers rf out rh ref r bias vp rh bias rl bias rw bias filter v bias (unbuffered) rf impedance matching c bulk class a example i dq ? v ref k 1 * r sense k 1 is fixed 50x for the internal comparator input. (1) ? v = i dq * r sense v out = k 2 * ? v k 2 is fixed to 20x for the vout pin x9470 13 fn8204.0 march 8, 2005 figure 2. sense and scale block diagram the wiper of the digital potentiometer acts like its mechanical equivalent and does not move beyond the last position. that is, the counter does not wrap around when clocked to either extreme. the electronic switches in the potentiometer operate in a ?make before break? mode when the wiper changes tap posi- tions. if the wiper is moved several positions, multiple taps are connected to the wiper for t iw (scl to rw bias change). when the device is powe red-up, the x9470 will load the last saved value from the non-volatile memory into the wcr. note that the current wiper position can be saved into non-volatile memory register by using the scl and cs pins as shown in figure 4. important note: the factory setting of the wiper counter register is the zero-position (0 of 255 taps). this is the default wiper position. bias adjustment block instructions and program- ming. the scl, inc/dec (internal signal) and cs inputs control the movement of the wiper along the resistor array. (see table 1) with cs set high, the device is selected and enabled to respond to the inc/dec and scl inputs. high to low transitions on scl will increment or decrement r bias (depending on the state of the inc/dec input). the inc/dec input is derived from the output of the comparator of the sense and scale block. storing bias resistor values in memory. wiper val- ues are stored to volatile memory automatically when cs is high and inc/dec either transitions from high to low or from low to high. wiper values are stored to non-volatile memory during byte write or as described in the following section. table 1. mode selection * when coming out of shutdown, the cs pin must be cycled once before bias adjustment is enabled. inc/dec rw ref rl ref rh ref v out v dd v sense+ r sense v sense? 10k ? 64-tap v ref comparator inc/dec ~1k ? precision i-amp cint~2pf 10% } ? v i dq rf pa out choke v gate rf pa in k 2 = 20x k 1 = 50x sda cs* scl inc / dec mode h h h vbias is incremented one tap position. h h l vbias is decremented one tap position. h h x lock wiper position. save to volatile memory. (biaslock?) x l x x open loop. or x9470 14 fn8204.0 march 8, 2005 figure 3. bias adjustment block diagram non-volatile store of the bias position the following procedure will store the values for the rref and rbias wiper positio ns in non-volatile mem- ory. this sequence is intended to be performed after a biaslock calibration sequence to simplify storage. if biaslock has not been achieved, then the rbias wiper position may change when the cs pin is brought high and scl begins clocking. see figure 4 for the actual sequence. 1. set the wel bit with a write command (02h to reg- ister 0fh) 2. peform a calibration and achieve biaslock. leave cs pin high. 3. write the address byte only (start, followed by device/slave address and a 0 for a write, see page 19). 4. perform a stop command. 5. with scl still low, bring the cs low. the falling edge of the cs will in itiate the nv write. the wel bit may be reset afterwards to prevent fur- ther nv writes. inc/dec function the inc/dec pin is an open-drain logic output that tracks the activity of the increment/decrement compar- ator. a logic high at inc/dec indicates that the i dq did not rise up to the desired setting indicated by v ref while a logic low at the inc/dec pin indicates that the idq is higher than the desired setting. inc/dec is used as an internal control signal as well. as an example, when inc/dec is low, the bias adjustment circuit block will start to move the rbias resistor wiper towards the rl bias terminal end when cs is high and scl is clocking. consequently, the v bias voltage will decrease, and the i dq decreases to meet the desired v ref setting. the inc/dec signal can also be used to detect a damaged rf power fet. for instance, if inc/dec stays high during and after a calibration sequence it may indicate that the rf power fet has failed. this indicator can also be used with a level sense on the v out pin to perform diagnostics. shutdown mechanism this hardware co ntrol shutdo wn pin (shdn) will pull the voltage of v bias to vss with an internal pull down resistor. when shutdown is disabled (v bias is active when shdn is low), the v bias voltage will move to the previous desired bias voltage. it will take less than a micros econd to enable the inter- nal output buffer depending on the loading condition at the v bias pin. output (v bias ) v bias is a buffered output of rw bias (wiper output). it can deliver a high current for driving up to typically 1nf capacitive loading with stable performance and fast settling time. gate bias op amp + ? rw bias rh bias rl bias legend external pin/signal internal node/signal scl cs 2 3 1 v bias (unbuffered) v bias shdn to ldmos gate 10k ? 256-tap r bias inc u/d cs inc/dec xdcp memory and control wcr (rbias) bias register non-volatile power-on recall (por) note: 1) wcr = wiper control register inc/dec is logic high or low from sense/scale block and is used to increment or decrement the rbias resistor (xdcp) to adjust the gate voltage. x9470 15 fn8204.0 march 8, 2005 a single pole filter should be placed in between the v bias output and the rf input signal to isolate any high frequency noise. figure 4. non-volatile store of the bias position x9470 principles of operation the x9470 is a bias contro ller that contains all the necessary analog components for closed-loop dc bias control of ldmos transi stors in rf applications. the x9470 provides a mechanism to periodically set dc bias operating points of class a or ab-type ampli- fiers to account for v gs drift and temperature varia- tions. the following is an example of x9470 operation. the x9470 incorporates an in strumentation amplifier, comparator and buffer amplifier along with resistor arrays and their associated registers and counters. the serial interface provides direct communication between the host and the x9470. this section provides a detailed example of how the x9470 can be used to cali- brate and dynamically set the optimum bias operating point of an rf power amplifier (see figure 5): ? state 0: power-on monitor mode ? state 1: dc-bias setting when no rf is present [calibration] ? state 2: calibration disable when rf is present ? state 3: pa standby mode . dynamic adjustment for v gs drift and temperature variation ? state 4: power off (shut down) mode [turn off the power amplifier] state 0: monitor mode the v out and inc/dec outputs of the x9470 can be used for monitoring and di agnostic purposes. since v out has a lower gain (20x, default) than the internal ia output, it can handle higher drain sense current while keeping the output belo w the rail. this allows nor- mal pa power monitoring, and over-current sensing us- ing an external comparator. the inc/dec pin can be monitored during calibration to see if there is no change, which indicates ldmos functional problems. note that the inc/dec status is also available in the status register for software status reads. state 1: dc-bias setting when no rf is present [calibration] at calibration, the dc bias operating point of the ldmos power amplifier must be set. as soon as the bias adjustment circuit block is enabled (cs enabled, sda high, and scl pulse provided), the x9470 will automatically calibrate the external power amplifier by continually sampling the drain current of the external power amplifier and make adjustments to the gate voltage of the amplifier (see figure 6). initiates high voltage write cycle t wr stored in non-volatile memory cs scl sda non-volatile write of r bias and r ref value using sda, scl and cs pins r bias non-volatile register set wel bit calibration and bias lock set address byte stop 1 2 3 4 5 x9470 16 fn8204.0 march 8, 2005 figure 5. operating modes x9470 when no rf signal is present, the instrumentation amplifier of the x9470 senses the drain current as a voltage drop, ? v, across an external drain r sense resistor. the ? v is amplified and compared to an external scaling voltage, v ref . any difference between ? v and v ref results in a resistive increment or decrement of the internal r bias potentiometer. the r bias potentiometer is used as a voltage divider with the rh bias and rl bias terminals setting the upper and lower voltage limits of the unbuffered rw bias voltage. the resolution of the r bias potenti- ometer resistor is 0.4% of the difference of voltage across the rh bias and rl bias terminals. the r total is typically 10k ? with 256-taps. so, for example, if the difference between the rh bias and rl bias terminals is 1.024v, then the step accuracy is 4mv. the voltage at the rw bias pin is then fed into the v bias voltage follower. the v bias pin is a buffered output that is used to drive the gate of an ldmos transistor. the scaling voltage, v ref , set by the r ref potentiom- eter, sets the calibrated operating point of the ldmos amplifier. on edge transitions of the inc/dec signal, the x9470 will latch the current wiper position - this is known as ?bias lock?? mode. this is shown in figure 6. when biaslock occurs, the comparator hysteresis will allow inc/dec to change state only after the ia output changes by more than 20mv. this will prevent toggling of the v bias output unless the drain bias current is con- stantly changing. state 2: dc-bias disable when rf is present (optional) when an rf signal is present, the x9470 is put into standby mode (open loop). the x9470 is in standby mode when the cs pin is disabled so that the r bias potentiometer holds the last wiper position. the pres- ence of an rf signal at the input of a class a or ab amplifier increases the current across the r sense resis- tor. over a period of time, the temperature of the ldmos also increases and the ldmos also experi- ences v gs drift. therefore the dc biasing point that was set during state 1 (calibration) is not optimal. adjustments to the gate voltage will need to be made to optimize the operation of the ldmos pa. this is done in state 3. choose vref to scale idq, perform calibration, state 1 state 2 state 3 state 4 pa transmit mode pa calibration mode pa standby mode pa off mode disable bias adjustment, recalibrate bias point for drift and temperature. rbias resistor will automatical ly increment or decrement for optimal operating point continuously turn off pa latch bias point for dc bias current in wiper counter pa enabled, vout and inc/dec monitored for status state 0 pa monitor mode x9470 17 fn8204.0 march 8, 2005 state 3: pa standby mode, dc bias adjustment [compensation for v gs drift and temperature variation] when the power amplifier is in standby mode the x9470 allows for dynamic adjustment of the dc bias- ing point to take into account both v gs drift and tem- perature variation. dynami c biasing is achieved with the x9470 by using the cs, and scl pins. for exam- ple, the scl pin can be a st eady clock and the cs pin can be used as a control signal to enable/disable the bias adjustment block. figure 6 illustrates how th e x9470 can be used for dynamic biasing. upon the presence of an rf signal, the cs pin is pulled low. this will prevent the x9470 from changing the v bias voltage during i dq peak cur- rents. once the rf signal is no longer present, the cs pin can be enabled (closed loop), sda high and the x9470 bias adjustment circuit moves the v bias volt- age (the gate voltage of the fet) to meet the average i dq bias point for optimum amplifier performance. state 4: power off mode during power saving or power-off modes the x9470 can be shut down via the shdn pin. this pin pulls the output of the v bias pin low. figure 6. dynamic biasing technique: automatic dc bias operating point adjustment state 0 monitor mode state 1 calibration (no rf present) state 2 rf present state 3 recalibrate bias point for drift and temperature state 4 shut down set operating range scale for bias adjustment rf signal v ref cs scl inc/dec shdn v bias 1 2 3 4 5 6 r bias default is zero point of r total latch r bias dc point in calibration vs v ref rf present turn off bias adjustment r bias increase/decrease after rf present due to temperature increase & v gs -threshold drift idq vs. gate voltage bias optimized shut down biaslock saves wiper position to volatile memory bias adjustment on bias adjustment off bias adjustment on automatic bias adjustment biaslock x9470 18 fn8204.0 march 8, 2005 x9470 status register (sr) and control register (cr) information table 2. status register (sr) status register (sr) the status register is located at address 0f 19 fn8204.0 march 8, 2005 x9470 bus interf ace information figure 7. slave address, word address, and data bytes - write mode figure 8. slave address, word address, and data bytes - read mode slave address, byte address, and data byte the byte communication format for the serial bus is shown in figures 7 and 8 above. the first byte, byte 0, defines the device indent ifier, 0101 in the upper half; and the device slave addr ess in the low half of the byte. the slave address is determined by the logic val- ues of the a0, a1, and a2 pins of the x9470. this allows for up to 8 unique addresses for the x9470. the next byte, byte 1, is the byte address. the byte address identifies a unique address for the status or control registers as shown in table 3. the following byte, byte 2, is the data byte that is used for read and write operations. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the st art condition and will not respond to any command until this condition has been met. see figure 9. slave address byte byte 0 d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte byte 2 a6 a5 0 10 s1 1 s0 r/w =0 s2 device identifier byte address byte 1 slave address 0fh : sr 00h : v bias 01h : v ref slave address byte byte 0 d7 d6 d5 d2 d4 d3 d1 d0 d0 d7 d2 d4 d3 d1 data byte byte 2 d6 d5 0 10 s1 1 s0 r/w s2 device identifier data byte byte 1 slave address x9470 20 fn8204.0 march 8, 2005 stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition ca n only be issued after the transmitting device has rel eased the bus. see figure 9. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during t he ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 10. the device will respond with an acknowle dge after recognition of a start cond ition and if the correct device identifier and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for: ? the slave address byte when the device identifier and/or select bits are incorrect ? the 2nd data byte of a status register write oper- ation (only 1 data byte is allowed) figure 9. valid start and stop conditions figure 10. acknowledge response from receiver figure 11. valid data changes on the sda bus scl sda start stop scl from master data output from transmitter data output from receiver 8 1 9 start acknowledge scl sda data stable data change data stable x9470 21 fn8204.0 march 8, 2005 write operations byte write for a write operation, the device requires the slave address byte and the word address bytes. this gives the master access to any one of the words in the array. upon receipt of each address byte, the x9470 responds with an acknowle dge. after receiving the address bytes the x9470 awaits the eight bits of data. after receiving the 8 data bits, the x9470 again responds with an acknowledge. the master then ter- minates the transfer by generating a stop condition. the x9470 then begins an internal write cycle of the data to the nonvolatile memory. during the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda output is at high impedance. see figure 12. a write to a protected block of memory is ignored, but will still receive an acknowle dge. at the end of the write command, the x9470 wi ll not initiate an internal write cycle, and will continue to ack commands. stops and write modes stop conditions that terminate write operations must be sent by the master after s ending at least 1 full data byte and it?s associated ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte + ack is sent, then the x9470 resets itself without performing the write. the contents of the array are not affected. acknowledge polling disabling of the inputs durin g nonvolatile write cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indi- cate the end of the master?s byte load operation, the x9470 initiates the internal nonvolatile write cycle. acknowledge polling can begin immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the x9470 is still busy with the nonvolatile write cycle then no ack will be returned. when the x9470 has com- pleted the write operation, an ack is returned and the host can proceed with the read or write operation. refer to the flow chart in figure 15. read operations there are three basic read operations: current address read, random read, and sequential read. current address read internally the x9470 contains an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read o peration would access data from address n+1. on power-up, the address is initial- ized to 0h. in this way, a current address read immedi- ately after the power-on reset can download the entire contents of memory starting at the first location. upon receipt of the slave address byte with the r/w bit set to one, the x9470 issues an acknowledge, then trans- mits eight data bits. the master terminates the read operation by not responding with an acknowledge dur- ing the ninth clock and issuing a stop condition. refer to figure 13 for the address, acknowledge, and data transfer sequence. x9470 22 fn8204.0 march 8, 2005 figure 12. byte write sequence figure 13. current address read sequence figure 14. random address read sequence s t a r t s t o p data a c k a c k sda bus signals from the slave signals from the master 0 a c k byte address 0 a0 a1 a2 0 1 0 1 slave address device id s t a r t s t o p data a c k sda bus signals from the slave signals from the master slave address 1 a0 a1 a2 0 1 0 1 device id a c k a c k s t a r t s t o p data s t a r t sda bus signals from the slave signals from the master byte address 0 a c k slave address 0 a0 a1 a2 0 1 0 1 device id a c k slave address 1 a0 a1 a2 0 1 0 1 device id a c k x9470 23 fn8204.0 march 8, 2005 figure 15. acknowledge polling sequence it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. random read random read operations allows the master to access any location in the x9470. prior to issuing the slave address byte with the r/w bit set to zero, the master must first perform a ?dummy? write operation. the master issues the star t condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipt of each word address byte , the master immediately issues another start conditi on and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit data word. the master terminates the read operation by not responding with an acknowledge and then issu- ing a stop condition. refer to figure 13 for the address, acknowledge, and data transfer sequence. in a similar operation called ?set current address,? the device sets the address if a stop is issued instead of the second start shown in figure 14. the x9470 then goes into standby mode after the stop and all bus activity will be ignored unt il a start is detected. this operation loads the new address into the address counter. the next current address read operation will read from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes issue stop no continue normal read or write command sequence proceed yes nonvolatile write cycle complete. continue command sequence? x9470 24 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8204.0 march 8, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 24-lead plastic, tssop package type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ?a? .031 (.80) .041 (1.05) 0 - 8 .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x) x9470 |
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